NETEDIT: Verilog
Netlist Viewer / Editor
NetEdit tool allows designers to edit post-synthesis Verilog netlist using an in-process TCL scripting approach.
First, a verilog file is parsed and stored in the internal database. Then, it can be viewed the same way as in a NetMan tool and edited using the set of netlist editing functions built in the TCL shell. After editing, the netlist can be regenerated in Verilog format again.
NetEdit User Guide : Instalation
NetEdit User Guide : Using Example Design
Design Tab Description
The following picture shows “Design” tab of Netedit Tool:
Design Menubuttons Description
There are the following menu buttons in “Design” Section:
- Load Design: Opens File Selection Dialog window in order to load Structural Verilog Design file.
- Load Library: Opens File Selection Dialog window in order to load Verilog Library file for the current design. In case of the multiple library files load them one after another.
- Load DB: Opens File Selection Dialog window in order to load Design Database file. As a result of Load_Design and Load_Library commands, Database file is generated in the same directory where Design file resides. In order to save time for processing verilog files, DB file can be loaded, if it exists.
- Load TCL file: Opens File Selection Dialog window in order to load TCL file which contains user-defined TCL procedures and programs
- Launch NESH: (Currently works under UNIX only): Launches interactive NetEdit TCL Shell (NESH) in a new window. Can be useful in order to develop user-defined procedures and scripts. NESH shell will work independently from the main NetEdit application. (See description of NetEdit functions in “Help Commands” section)
- Help Commands: Get help for NetEdit functions. Clicking on this button, the Commands Help window will appear:
Double Click on the selected command in order to get the command description.
Design Tab Description
· Select Top Module: Select top design module using this combobox. Initially, this combobox is empty. Module names appear inside it only after you load a design using the “Load Design” and “Load Library” or “Load DB” commands. Choose top design module in this combobox after loading design in order to se design modules tree inside “Modules Tree” widget.
· Modules Tree: Represents a Module tree hierarchy of the loaded design. Double click on the selected module to make it active (equivalent to the “mod set <module_name>” command)
· Commands prompt: Type one-line TCL commands in this prompt and finish with the <Return> key. A command output will appear inside the “Output Log” window. Stores commands history inside prompt’s combobox.
· Scripts Input: Develop your TCL scripts inside this widget. In order to run one or more lines of code, select lines with left mouse button and then click on “Run” button.
· Output Log: All command outputs are redirected to this widget. Use “Clear” button to clean it. Use “Find” button in order to search for needed pattern (enter pattern in “Command Prompt” entry and click on “Find” button I order to locate this pattern in the Output Log window)
Netlist
Tab Description
The following picture shows “Netlist” tab of Netedit Tool:
This window is based on the same concepts as “NetMan” and “SynView” netlist viewers. Use this tab only after selecting one of the modules to be “active”, double-clicking on it in the “Modules Tree” window (the name of an “active” module appears in the left top corner of a graphical widget). The main guidelines for this tab are listed below:
· Widget starts from empty window.
· First, select type of elements to locate inside “Type” ComboBox
· Second, (optionally) enter the pattern in order to narrow the search
· Clicking on “Search” button will fill “Results:” combobox with result data.
· Choosing on of results will put graphical represenation of this element on the screen.
· Clicking with left mouse button on selected pin of this element will show all design elements, connected to this pin.
· Move design element with right mouse button, delete them (from viewer only, not from design) pointing on them with mouse cursor and pressing on “delete” key.
Note, this is a Netlist Viewer only. Design Connectivity can only be edited using TCL scripts with built-in commands.
The main improvement of this viewer over the previous, used in “NetMan” and “NetEdit” tools is Buses support. Clicking on “bused” pin will open another bit selection listbox window, where needed bit could be selected.
NetEdit
User Guide: Instalation
Netedit tool can run smoothly as on UNIX so on Windows operating system.
Running NetEdit with Windows:
· Download and install TCL interpreter for Windows: http://prdownloads.sourceforge.net/tcl/tcl832.exe
· Unpack the contents of NetEdit; double click on “netedit.tcl” to launch the tool.
Running NetEdit with Linux:
· Unpack the contents of NetEdit.tar.gz file
· Set environment variable “NETEDIT_PATH” to the “netedit” installation directory
· Launch netedit.tcl file
Running NetEdit with other Unix Operating Systems:
· Unpack the contents of NetEdit.tar.gz file
· Set environment variable “NETEDIT_PATH” to the “netedit” installation directory
· Compile tclsqlite.so executable, following instructions found in netedit/tclsqlite/Readme file
· Launch netedit.tcl file
NetEdit
User Guide: Using Example Design
First, click on Design -> Read Verilog menubutton to load example/i2c.v file
Then, click on Design -> Read Lib menubutton in order to load example/lib.v file
As a result, new database file, i2c.db will be created in the same “example” directory.
Then, choose top module (i2c in our case) in the combobox under the modules tree widget. Modules hierarchy will appear inside “Modules Tree” widget. Click on chosen module (for example, on i2c) to make it active.
Explore the connectivity of this module using Netlist Tab window.
Enter commands into the command entry of Design Tab in order to explore/edit netlist.
NetEdit
Built-in Commands
MODULE Commands
mod get
mod get [<pattern>]
Returns list of module names that
match the specified pattern.
If pattern is not specified, returns
all module names
Example: mod get i2c* ->
{i2c i2c_controller ...}
mod set
mod set [<module_name>]
If argument exists, sets given module
to be current (Example: current i2c)
Without argument, returns name of
current module
Example: mod set i2c
mod submods
mod submods [<pattern>] [-lib|-mod]
Returns submodules of current module
that match spesified pattern.
Use -lib switch in order to get library
modules names only. Use -mod switch in
order to get hierarchical modules names.
By default, all modules will be searched.
Example: mod submods * -lib ->
{NAND2X2 INVX2 NOR2X2 ....}
mod rm
mod rm <module_name>
Removes module with specified name.
Returns 1 in a case of success, else 0.
Example: mod rm i2c -> 1
mod new
mod new <name>
Creates new module. Returns 1 in a case of
success, else 0. Module name should be unique.
Example: mod new bit_controller -> 1
mod write
mod write <file_name>
Writes current module in verilog format
into specified file
CELL Commands
cell get
cell get [<pattern>]
Returns list of instance names in
current module that match given pattern
If pattern is not specified, returns
all instances in current module
Example: cell get U12* -> {U121 U122 ...}
cell pins
cell pins <iname> [-in|-out] [-full]
Returns pins list of cell with given instance
name. Use -in or -out to specify pins direction.
By default both pin directions are taken.
Use -full option to get pins name with
<cell_name>/<pin_name> format (By default, only
pin names are returned)
Example: cell pins I12 -in -full -> {I12/A I12/B}
cell mod
cell mod <instance_name>
Returns module name of specified cell.
Example: cell mod I123 -> NAND2X2
cell rm
cell rm <instance_name>
Removes cell with specified instance
name from current design. Returns 1 in
a case of success, else 0.
Example: cell rm I123 -> 1
cell new
cell new <instance_name> <reference_name>
Creates cell instance with given instance
and reference names. Returns 1 in a case
of success, else 0. Instance name should be
unique for current module.
Example: cell new I232 NAND2X2 -> 1
PORT Commands
port get
port get [<pattern>] [-in|-out] [-split]
Returns ports list of current module
that match specified pattern.
Use -in or -out to specify ports direction.
By default both port directions are taken.
Use -split option to split bused ports.
Example: port get PB* -in -> {PB_EN PB DATA ..}
port rm
port rm <net_name>
Removes port with specified port
name from current design. Returns 1 in
a case of success, else 0.
Example: port rm SCAN_EN -> 1
port new
port new <name> <-in|-out>
Creates port with specified name and direction
in current module. Returns 1 in a case of
success, else 0. Port name should be unique for
current module.
Example: port new PX_EN -in
PIN Commands
pin parent
pin parent <full_pin_name>
Returns name of parent cell if specified
pin exists.
Example: pin parent I123/A -> I123
pin net
pin net <pin_name> [bit_number]
Returns net name connected to specified
pin. Pin should be specified using
<cell_name>/<pin_name> format.
For bused pin, specify bit number.
Example: pin net I12/Y -> NET23
pin exists
pin exists <pin_name>
Returns 1 if specified pin
exists in current module. Else,
returns 0. Pin should be specified
using <cell_name>/<pin_name> format.
Example: pin exists I23/A -> 1
NET Commands
net get
net get [<pattern>]
Returns list of nets in current
module that match specified pattern
If pattern is not specified, returns
all net names
Example: net get NET1* ->
{NET12 NET13 NET14 ...}
net pins
net pins <net_name> [-in|-out]
Returns pins connected to specified net.
Use -in or -out to specify pins direction.
By default both pin directions are taken.
Example: net pins NET12 -out ->
{I12/B I23/A}
net connect
net connect <net_name> <pin|port name>
Connects specified net to pin or port.
Returns 1 in a case of success, else 0.
Pin should be specified using
<cell_name>/<pin_name> format.
Example: net connect Net123 I12/A -> 1
net disconnect
net disconnect <net_name> <pin|port name>
Disonnects specified net from pin or port.
Returns 1 in a case of success, else 0.
Pin should be specified using
<cell_name>/<pin_name> format.
Example: net disconnect Net123 I12/A -> 1
net rm
net rm <net_name>
Removes net with specified name from
current design. Returns 1 in a case of
success, else 0.
Example: net rm NET23 -> 1
net new
net new <net_name>
Creates net with specified name in current
module. Returns 1 in a case of success, else
0. Net name should be unique for current
module.
Example: net new NET132 -> 1
LIB Commands
lib get
lib get [<pattern>]
Returns list of module names in
loaded library that match given pattern
If pattern is not specified, returns
all instances in current module
Example: lib get NAND* ->
{NAND2X2 NAND2X4 ...}
lib pins
lib pins <lib_module_name> [-in|-out]
Returns pins list of specified library cell.
Use -in or -out to specify pins direction.
By default both pin directions are taken.
Example: lib pins NAND2X2 -in -> {A B}
lib rm
lib rm <module_name>
Removes library module with specified
name. Returns 1 in a case of success,
else 0.
Example: lib rm NAND2X2 -> 1
COMMON Commands
lget
lget <list> <regexp>
Returns sublist of given list that matches
give regular expression
Example: lget {123 234 452} *23* -> {123 234}
help
help <expression>
Returns list of existing TCL procedures (commands)
which match predefined expression
Example: help p -> {port pin}
read_verilog
read_verilog <verilog file>
Reads verilog file into internal database
read_lib
read_lib <verilog library file>
Reads verilog library file into internal
database
read_db
read_db <database file : *.db>
Reads existing database file
link
link
Links hierarchical design
and reports about unresolved modules.
Choose current module to be the to one
in order to link the whole design.
write_all
write_all <file_name>
Writes all modules in verilog format
into specified file