DFT Scripting Methodology

In order to run an internal scan insertion, users must have free licenses for Synopsys Test Compiler. Even a basic design compilation with a –scan switch requires this license. The following article presents methodology and provides free scripts in order to insert scan without the Test Compiler.

Compilation with Scan Registers

Running compilation with a –scan option provides more realistic timing results. During this compilation, non-scannable flip –flops are replaced by corresponding scannable ones. The following picture demonstrates how Synopsys Design Compiler replaces and reconnects scannable flip-flops:

A Scannable Flip-Flop has two additional inputs, compared to the regular one. Usually, the input names are SD (scan data) and SE (scan Enable). When Design Compiler inserts a scannable Flip-Flop, it connects SE input to “Logic 0” and SD – to the same Flip-Flop output pin. Connecting SE to logic 0 sets Flip Flop to work in the functional mode, permanently selecting “D” input. Connecting SD pin to the same Flop’s Q pin adds one more fanout to the net, connected to the Q pin, making timing analysis of the network to be exactly the same as for the design with inserted scan chains. Then Design Compiler tries to close timing on existing network.

The only one, but important, drawback of the command “compile –scan” is that this command requires both the Design Compiler and Test Compiler licenses.

However, scannable registers insertion and proper connection can be done without Test Compiler at all. The following steps explain this process:

§ Download regscan.tcl script.

§ Run compilation without –scan switch. Non-scannable Flip-flops will appear in design.

§ Load regscan.tcl script into design compiler and run replace_regs command (refer to regscan script comments for usage details). This script will replace non-scannable flip-flops with corresponding scannable ones and connects them in the same way as Design Compiler does.

§ Finally, run compile –incremental –map_effort low in order to finish timing optimization on design with scannable flip-flops.