Effective Synthesis Methodology Using Synopsys
DC
Synopsys tools are very powerful, flexible, and
configurable. However, additional work is required in order to start using them
efficiently and to integrate them into your design process. In this article, I
present a methodology which I developed while working at Tundra Semiconductors.
This methodology is project-independent and is suited for both synthesis gurus
and designers who don’t want to spend additional time to set up the tools and
explore various options and switches.
This
article contains four different topics. All of them are building blocks of this
synthesis methodology. First of all, pre-synthesis tools and methodology are
described. Using these tools, block designers can run technology-independent
synthesis and check RTL code for synthesis problems in a push-button manner.
Then, synthesis methodology is presented. It is based on the set of highly configurable
and well-documented TCL procedures. Using these procedures, highly configurable
synthesis environments can be created.
Then, a
top-level creation methodology is described. Usually, designers create a
top-level design with buffer instantiations manually, especially when custom IO
buffers are used, and it is a time-consuming and error-prone process. In our
case, the top-level design is created automatically. Port types, connections,
and module instantiations for the chip-level design are defined automatically.
Script takes as an input Functional Logic interface that follows
straightforward and simple naming convention rules. Finally, bi-directional
pipelining TCL technique is presented. Using this technique, graphical
applications/widgets can be opened directly from the “dc_shell-t” prompt. Some
of the visual applications, based on this technique, are described.
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