# Auxiliary
Function
#------------------------------------------------------
proc c2l
{collection} {
set my_list {}
foreach_in_collection coll_element
$collection {
set element [get_object_name
$coll_element]
lappend my_list $element
}
return $my_list
}
#------------------------------------------------------
# Auxiliary
function:
# Deletes
list or value from the other list
# Arguments
: initial list and list (or value) to delete
# Return
value : part of initial list with values which are
# different
from the values in the list_to_delete
#------------------------------------------------------
proc ldelete
{list list_to_del} {
foreach str $list_to_del {
set ix [lsearch -exact $list $str]
if {$ix >= 0} {set list [lreplace $list
$ix $ix]}
}
return $list
}
#------------------------------------------------------
# Loads db
files from "db_dir" directory
# into
Synopsys memory
#------------------------------------------------------
proc load_db_files
{db_dir} {
set dbfiles [exec ls $db_dir]
foreach dbfile $dbfiles {
if {[regexp {[^ ]*\.db} $dbfile m]} {
read_db $db_dir/$dbfile
}
}
}
# Loads
verilog design files reading corresponding "vfiles"
#---------------------------------------------------------
proc load_vfiles
{vfiles} {
set vdir [file dirname $vfiles]
set VF [open $vfiles r]
while {[gets $VF line] >= 0} {
if {[regexp {^[ ]*([^ ]+)} $line m vfile]} {
read_verilog $vdir/$vfile
}
}
close $VF
}
# Run
Synthesis
# This
function requires existence of the following directory structure:
#
constr_tcl: contains common.tcl functions and design-specific constraints
# syn_db :
synthesised design will be stores in this directory
# reports :
synthesis log will be stored in this directory
# Please,
refer to my SNUG Article for details and usage examples
#------------------------------------------------------
proc run_syn
{design vfiles} {
load_vfiles $vfiles
current_design $design
if {[link]} {
uniquify
ungroup -all -flatten
remove_design [remove_from_collection
[get_designs] [current_design]]
source constr_tcl/common.tcl
if [file exists constr_tcl/$design.tcl] {
source constr_tcl/$design.tcl
}
compile -scan > reports/$design.syn
write -hier -o syn_db/$design.db
remove_design -designs
} else {
echo "Error linking design
$design"
}
}
# Checks
design for correct linkage
#------------------------------------------------------
proc run_link
{design vfiles} {
load_vfiles $vfiles
current_design $design
if {[link]} {
echo "Design $design linked
successfully" >> link.rep
} else {
echo "Error linking design
$design" >> link.rep
}
}
# Checks
for unexpected latch insertion in design
#------------------------------------------------------
proc check_latch
{vfile} {
read_verilog $vfile > tmpfile
set TF [open tmpfile r]
set flag 0
while {[gets $TF line] >= 0} {
regexp {in routine ([^ ]+) line ([0-9]+) }
$line m mod_name lnum
if {[regexp {^\|[ ]+([^ ]+)[ ]+\|[
]+Latch} $line m lname]} {
echo "Found latch $lname in module
$mod_name, line $lnum"
}
}
close $TF
exec rm tmpfile
}