Contents

create_tb: Creates testbench wrapper for block-level simulation

change_module_names: changes module names throughout hierarchy adding to all module names specified prefix

Name

create_tb

Synopsis

create_tb <dut_module_name> <verification wrapper name>

Description

This script creates verification wrapper for given Verilog module in the following way:

The instance of <dut_module> is created inside wrapper module

For each <dut_module> input, corresponding register is created and connected to the <dut_module> input pin

For each <dut_module> output, corresponding wire is created and connected to the <dut_module> output pin

Example:

module example (A, B, C, D); input [0:12] A; input B; output [0:12] C; ===> output D; endmodule

module example_test (); // Inputs - to registers reg [0:12] A; reg B; // Outputs - to wires wire [0:12] C; wire D; //Core Module Instantiation example example ( .A (A), .B (B), .C (C), .D (D) ); endmodule

Source code

Name

change_module_names

Synopsis

change_module_names –add_prefix <prefix> | -del_prefix <prefix>

Description

This script changes module names in given verilog files, solving the problem of multiple module definition in Verilog. Run script with –add_prefix <prefix> option in order to add specified prefix to all module names. New module names will be: <prefix>_<original_module_name>; changes affect module declarations statements and module instantiations. In order to delete previously defined prefix run this script with –del_prefix <prefix> switch. All verilog files should reside in the same directory.

Note: Script works properly with tclsh versions 8.2+. In the cases of problems, please edit the first line of script in order to point to your tclsh executable.

Source_code